Term |
Definition |
| AMP |
HP-Compaqs Concept Advanced Memory Protection
includes functions Hot Spare Memory , Memory Mirroring and Advanced ECC-Chipkill
|
| Chipkill |
IBM
Chipkill™is a development of the main memory error correction code ECC, that
is able to compensate the failure of a total memory chip.
In the original version Chipkill runs with a
128-bit- memory bus with 16 redundant bits (two 64bit-buses with ECC) only for x4-organised memory chips.
Intel also calls this memory error correction method x4 Single Device Data Correction (SDDC). In the meantime, Chipkill is possible on some chipsets
for x8-chips as well. Chipkill is being supported by server manufacturers as Acer,
Apple, Dell, Fujitsu-Siemens,
Silicon Graphics und Sun.
See also:
Chipkill™ - Data security today »» CompuRAMPressemitteilung (PDF-Dokument)
|
| DDR |
Double Data Rate (DDR)
DDR memory is the next generation of the present SDRAM memory. The DDR memory is based
on the same design as SDRAM principially, but with the difference, that on the DDR memory data are being read on both edges of a clock cycle.
Due to that, the bandwith is being doubled in comparison to generic-SDRAMs. Hence the data on a data bus can be submitted without increasing the clock speed with twice as much
speed in comparison to SDRAM. Common speeds are DDR266
- PC2100DDR333
- PC2700 und DDR400 - PC3200
|
| DDR2 |
A development of the DDR-SDRAM concept is DDR2-SDRAM memory. On
the DDR2 memory the memory cache has been increased from 2- to 4-times prefetch units.
|
| Dual Channel |
Simply said, a Dual Channel configuration doubles your systems theoretic data transfer rate in comparison to Single Channel mode.
This happens by bundling a compatible module pair in connection with a
parallel memory access to both memory channels. Please note the different
requirements for the usage: Dual Channel DDR or Dual Channel DDR2 and DDR3
|
| DDR3 |
The DDR3-SDRAM
concept uses eight (instead of four) simultaneously adressable memory slots for a more effective
data processing. The arrangement of the chip pins has been optimized for higher clock rates. The supply voltage
is 1.5 Volt. The memory cache has been increased from 4- to 8-times prefetch units.
Due to that, the chips
can run with half of the clock internally. This reduces the power loss but increases the waiting times between
the request and the delivery of the memory content(CAS latency).
|
| DIMM |
Dual In-line Memory Module
DIMM modules and SIMM modules differ mainly in the contacts of the pins.
On the DIMM modules the pins are on the opposite sides of the module
independently from each other and build two contacts.
The pins on each side of the SIMM module are connected and build a contact.
One differs between 168pin
SDRAM, 184pin
DDR and 240Pin DDR2.
|
| DRAM |
Dynamic Random Access Memory
The Dynamic Random Access Memory is the most commonly used way of the system memory.
The DRAM memory is able to receive and save a certain data load only for a short period of time.
To keep the data, the DRAM must be refreshed regularly, if not, the data will be lost.
|
| ECC |
Error Correction Code
The Error Correction Code is a method to check the integrity of the data in the DRAM.
This method can determine and correct more-bit errors as well as single-bit errors. In
comparison to parity check, ECC is a more complex error determination method.
|
| EDO |
Extended Data Output Memory
On computers with EDO memory the CPU can access the memory 10- 15% faster as when using comparable chips that use FPM
(Fast Page Mode). This is being made possible by a type of DRAM technology that advances the reading access.
|
| FLASH |
A Flash memory is a so called non-volatile memory, that needs power for
reading and writing. For the stable preservation of data no power is needed. Due to that the
power consumption is lower. However, in comparison to conventional DRAM memory, reading and writing on
non-volatile memory is slower.
Flash-Memory are to be found mainly in digital cameras and MP3 players, camcorders and printers, notebooks
and handhelds. They can also be used as memory cards for desktops and as well
for a quick cache for connecting to mainframes.
|
| Flex Mode |
This new Dual Channel technology offers highest flexibility when installing
memory modules. So to say, it voids almost every current limits and requirements
to the memory modules. The Dual Channel mode also works when only 2, 3 or
4 DIMMs with different total capacity are installed in the memory channels.
|
| FPM |
Fast Page Mode
This is a common DRAM type. With Fast Page memory, the processor of the computer
can access new data in half of the time, if they are on the same side as the former read data.
|
| Fully-Buffered (FB-DIMMs) |
The Fully-Buffered technology is a new memory bus technology
that could solve the speed and capacity problems
of common Registered-DDR2 memory modules.
Central unit of this new memory architecture is the Advanced Memory Buffer (AMB),
that takes over the buffering and deployment of the data between the single memory chips on the module.
Thereby the data processing does not take place parallel anymore.It is now serial, via point-to-point connections between the memory controller and
the first chip as well as between the single chips.
Due to that, the memory capacities as well as the memory speeds can be increased many
times over. Furthermore this memory architecture enables a better scalability and
flexibility and offers extensive data security features.
Please see:
CompuRAM - Compatible memory upgrades now also with fully-buffered technology
»
Press information (PDF document)
Common speed for INTEL chipsets
is DDR2-667
- PC2-5300 FB - ECC - Fully Buffered
|
| Hot Spare Memory |
(also: DIMM Sparing or online surrogate memory)
For the Hot Spare Memorytechnology,
a definded memory bank is available as a substitute. If a memory controller determines
frequent memory errors on a module, it will deactiviate the bank with the defect module and then activate the surrogate memory bank
automatically. The Hot Spare module is being switched on automatically
and therefore there will be no data loss during the running operations.
|
| Northbridge |
Northbridge is the name of a memory controller and the connection in form of the front side bus between
main memory, cache and CPU.
AMD integrates this Northbridge on their server
and workstation chipsets into the CPU.
|
| Memory Mirroring |
The 1:1 Memory Mirroring requires two identica memory modules
in two different banks. The memory controller hides the mirrored memory automatically
and works with only one active memory. If the memory controller determines frequent errors
in the active memory area, it switches to the mirrored area during the running operations without data
loss. The disadvantage of memory mirroring is that the usable total memory is being
halved.
|
| Memory Scrubbing |
The Memory Scrubbing is able to, independently of the operating system, preventively
run an automated memory test. Though Memory Scrubbing requires an activated
ECC function of the chipset. In the scope of the memory test, memory errors will be checked and,
if neccessary, security relevant functions as Memory Mirroring or ProteXion are being started. Thereby
server breakdowns due to memory errors shall be avoided. The results of the memory test
will be forwarded to the server management software.
|
| Parity |
The parity check is a process for identifying errors during the
data transmission. Next to the 8-data bits an additional 9th check bit resp. parity bit
is set from the sender and is being analysed by the receiver.
|
| RAM |
Random Access Memory In computers RAMs are being used by the central units (CPU) as memory
or main memory,which they can access randomly. This
means that every byte can be accessed directly, without any reference to the former or next
byte. In a RAM - in opposite to ROM (= Read Only Memory), can be accessed randomly with writing and reading.
The new data will be saved in a RAM as long as
it will be overwrited by new data and as long as the RAM is being provided with supply voltage.
The access times of RAMs are in nanoseconds-scope.
One differs between static SRAM
and dynamic DRAM. On the static RAM, the information is being maintained after writing for
a longer time, on the dynamic RAM the written information volatiles
after split-seconds and therefore has to be refreshed permanently.
|
| RAMBUS |
Rambus® Dynamic Random Access Memory
Rambus® DRAM is an asynchronous DRAM, that has been developed by the US company Rambus
Corporation and has been launched by Intel as succession technology of SDRAM for memory in the whole
computer market. But instead of RDRAM, DDR-SDRAM became the SDRAM succession in the DRAM mass market and Rambus®
DRAM could only assert itself in certain applications. As a common type one can name 184pin
RIMM 800 Mhz and 184pin RIMM 800 Mhz - ECC. In the graphics card market, the Rambus technology
is still being used.
|
| Rank |
The Term „Rank”
was established by JEDEC (Joint Electron Device Engineering
Council). A Memory Rank, also called
memory row, is a 64 bit wide data scope of a memory module, that can be addressed
singularly. Depending on with what DRAM chips a DIMM is being made, it can contain 1, 2 or 4 Ranks.
Accordingly it is called Single-, Dual- or Quad-Rank-module. If
the correct module type is not chosen, it could
cause problems on later memory upgrades. Also there is a close relation between the number of the
Memory Ranks and the memory speed of the server.
|
| Registered DIMM |
Registered DIMMs have special driver modules (Register-ICs),
that edit the address- and data signals of a memory module and forward them to the memory chips.
On common unbuffered modules all signal lines are switched parallel and lead directly
to the memory modules. Where high memory capacities are mandatory, unbuffered memory modules
might strain the signals too much and cause errors.
A disadvantage of the Registered-DIMM-technology
is the time delay that arises because of the clock for the signal refreshing. However,
the advantage of a more stable system in the server surrounding compensates these performance losses. Offered
as 168pin,
184pin
for Intel
resp. AMD)
and 240pin DDR2 und 240pin DDR3.
|
| SDDC |
Single Device Data Correction
On x4-DDR memory Intel offers x4 Single Device Data Correction (x4 SDDC) a data identification
and -correction for 1, 2, 3 or 4 bits within the same memory chip and a data identification
up to 8 bits within two memory chips.
|
| SDRAM |
Synchronous Dynamic Random Access Memory
The SDRAM mode uses a clock generator
to synchronise the signal in- and output on a memory chip. The clock generator on the
memory chip is coordinated with the clock generator of the CPU, thus the time lapse of the memory chips
and the CPU are being synchronised. This mode reaches a time saving on the processing of
orders and transmission of data. Thus with a SDRAM, the CPU can access the memory about 25% faster as with an
EDO memory.
|
| SIMM |
strong>Single In-line Memory Module
A SIMM is being inserted into the memory slot
of the computer. SIMMs can be installed very easy and, in comparison to the horizontally installed
DRAMs, only have a minimal space demand.
|
| SO-DIMM |
Small Outline Dual In-line Memory Module
A SO-DIMM is approximately half as long as a 72pin SIMM and is an extended
version of a standard DIMM. Due to the small size, this concept is used in
industry-PCs and notebooks by these manufacturers Acer,
Apple, Dell,
Fujitsu-Siemens,
HP-Compaq,
Lenovo,
Siemens,
Sony und
Toshiba
.
|
| unbuffered |
On common unbuffered-modules all signal lines are switched parallel and
lead directly to the memory modules. Where high memory capacities are mandatory, unbuffered memory modules
might strain the signals too much and cause errors.
Therefore unbuffered modules are used preferably in desktops by Acer,
Apple,
Dell,
Fujitsu-Siemens,
HP-Compaq,
IBM,
Lenovo
.
|
Used logos, product and brand names might be proprietary names from our manufacturers and are only used for identification purposes.
